RTL8110S-64 参数 Datasheet PDF下载

RTL8110S-32/RTL8110S-64

Datasheet

Software can read and write to the EEPROM using “bit-bang” accesses via the 9346CR Register. The interface consists of

EESK, EECS, EEDO, and EEDI.

Table 10.

EEPROM

EECS

EESK

EEDI/Aux

EEPROM Interface

Description

93C46 (93C56) chip select

EEPROM serial data clock

Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.

This pin should be connected to Boot PROM. To support wakeup from ACPI

D3cold or APM power-down, this pin must be pulled high to aux. power via a

resistor. If this pin is not pulled high to Aux. Power, the RTL8110S assumes that no

Aux. Power exists.

Output data bus

EEDO

6.7. Power Management

The RTL8110S is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class

Power Management Reference Specification (V1.0a), such as to support an OS-directed Power Management (OSPM)

environment.

The RTL8110S can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via

PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs.

When the RTL8110S is in power down mode (D1 ~ D3):

•

The Rx state machine is stopped, and the RTL8110S monitors the network for wakeup events such as a Magic Packet,

Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8110S will not

reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO buffer.

•

•

•

The FIFO status and packets that have already been received into the Rx FIFO before entering power down mode are held

by the RTL8110S.

Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.

After restoration to a D0 state, the RTL8110S transfers data that was not moved into the Tx FIFO buffer during power down

mode. Packets that were not transmitted completely last time are re-transmitted.

The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space

depend on the existence of Aux power (bit15, PMC) = 1.

If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0's.

Example:

If EEPROM D3c_support_PME = 1:

•

•

If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC

(if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)

If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s

(if EEPROM PMC = C2 F7, the PCI PMC = 02 76)

Integrated Gigabit Ethernet Controller

18

Track ID: JATR-1076-21

Rev. 1.4