32192 参数 Datasheet PDF下载

8

8.3.2 Port Direction Registers

P0 Direction Register (P0DIR)

P1 Direction Register (P1DIR)

P2 Direction Register (P2DIR)

P3 Direction Register (P3DIR)

P4 Direction Register (P4DIR)

P6 Direction Register (P6DIR)

P7 Direction Register (P7DIR)

P8 Direction Register (P8DIR)

P9 Direction Register (P9DIR)

P10 Direction Register (P10DIR)

P11 Direction Register (P11DIR)

P12 Direction Register (P12DIR)

P13 Direction Register (P13DIR)

P15 Direction Register (P15DIR)

P17 Direction Register (P17DIR)

P22 Direction Register (P22DIR)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.3 Input/Output Port Related Registers

<Address: H’0080 0720>

<Address: H’0080 0721>

<Address: H’0080 0722>

<Address: H’0080 0723>

<Address: H’0080 0724>

<Address: H’0080 0726>

<Address: H’0080 0727>

<Address: H’0080 0728>

<Address: H’0080 0729>

<Address: H’0080 072A>

<Address: H’0080 072B>

<Address: H’0080 072C>

<Address: H’0080 072D>

<Address: H’0080 072F>

<Address: H’0080 0731>

<Address: H’0080 0736>

b0

(b8

Pn0DR

0

1

9

Pn1DR

0

2

10

Pn2DR

0

3

11

Pn3DR

0

4

12

Pn4DR

0

5

13

Pn5DR

0

6

14

Pn6DR

0

b7

b15)

Pn7DR

0

Note: • n = 0–13, 15, 17, 22 (not including P5)

<Upon exiting reset: H’00>

b

0(8)

1(9)

2(10)

3(11)

4(12)

5(13)

6(14)

7(15)

Bit Name

Pn0DR

Port Pn0 direction bit

Pn1DR

Port Pn1 direction bit

Pn2DR

Port Pn2 direction bit

Pn3DR

Port Pn3 direction bit

Pn4DR

Port Pn4 direction bit

Pn5DR

Port Pn5 direction bit

Pn6DR

Port Pn6 direction bit

Pn7DR

Port Pn7 direction bit

Notes: • Following bits are not provided (read as 0, writing has no effect):

P40, P60, P64–P67, P80, P81, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223,

P226, P227

• All ports are set for input mode upon exiting the reset state.

• P221 is an input-only port. Fix it to "0" when write.

• After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to

"1" (input enable), pin level can be read after 2BCLK period.

Function

0: Input mode

1: Output mode

R

R

W

W

32192/32195/32196 Group Hardware Manual

Rev.1.10 REJ09B0123-0110 Apr.06.07

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