HD74LVC74
Dual D-type Flip Flops with Preset and Clear
REJ03D0347–0400Z
(Previous ADE-205-066C (Z))
Rev.4.00
Jul. 22, 2004
Description
The HD74LVC74 has independent data, preset, clear, and clock inputs Q and
Q
outputs in a 14 pin package. The logic
level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset
and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high-
speed operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±24 mA (@V
CC
= 3.0 V to 5.5 V)
Ordering Information
Package Type
SOP–14 pin (JEITA)
TSSOP–14 pin
Package Code
FP–14DAV
TTP–14DV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LVC74FPEL
HD74LVC74TELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
H:
L:
X:
↓
:
↑
:
Q
0
:
Note:
CLR
H
L
L
H
H
H
H
H
CK
X
X
X
↑
↑
L
H
↓
D
X
X
X
H
L
X
X
X
Outputs
Q
H
L
H
*1
H
L
Q
0
Q
0
Q
0
Q
L
H
H
*1
L
H
Q
0
Q
0
Q
0
High level
Low level
Immaterial
High to Low transition
Low to high transition
Level to Q before the indicated steady input conditions was established.
1. Q and
Q
will remain high as long as preset and clear are low, but Q and
Q
are unpredictable, if preset and
clear go high simultaneously.
Rev.4.00 Jul. 22, 2004 page 1 of 6