HD74LS164
8-Bit Parallel-Out Serial-in Shift Register
REJ03D0448–0200
Rev.2.00
Feb.18.2005
This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit
complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the
first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them
determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but
only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of
the clock input.
Features
•
Ordering Information
Part Name
HD74LS164P
HD74LS164FPEL
HD74LS164RPEL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
SOP-14 pin (JEDEC)
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
PRSP0014DF-B
(FP-14DAV)
PRSP0014DE-A
(FP-14DNV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Serial
Inputs
A
B
Q
A
Q
B
1
A
2
3
4
5
6
7
B
Q
A
Q
B
Q
C
Q
D
CK
Q
H
Q
G
Q
F
Q
E
CLR
14
13
12
11
10
9
8
V
CC
Q
H
Q
G
Outputs
Q
F
Q
E
Clear
Clock
Outputs
Q
C
Q
D
GND
(Top view)
Rev.2.00, Feb.18.2005, page 1 of 8
RENESAS [ RENESAS TECHNOLOGY CORP ]
