HD74LS42
BCD-to-Decimal Decoder
REJ03D0409–0300
Rev.3.00
Jul.22.2005
This monolithic decimal decoder consists of eight inverters and ten four-input NAND gates. The inverters are
connected in pairs to make BCD input data available for decoding by NAND gates. Full decoding of valid input logic
ensures that all outputs remain off for all invalid input conditions.
Features
•
Ordering Information
Part Name
HD74LS42P
HD74LS42FPEL
HD74LS42RPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
0Y
1Y
2Y
Outputs
3Y
4Y
5Y
6Y
GND
1
0
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
D
C
B
A
16
15
14
13
12
11
10
9
V
CC
A
B
Inputs
C
D
9Y
8Y
7Y
Outputs
(Top view)
Rev.3.00, Jul.22.2005, page 1 of 6
RENESAS [ RENESAS TECHNOLOGY CORP ]
