Rev.1.1
Mitsubishi microcomputers
M3062GF8NFP/GP
Timers’ functions for three-phase motor control
Triangular wave modulation
To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit
(bit 6 at 0348
16
). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 0349
16
). In this mode, each
of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the
counter every time timer B2 counter’s content becomes 0000
16
. If “0” is set to the effective interrupt
output specification bit (bit 1 at 0348
16
), the frequency of interrupt requests that occur every time the timer
B2 counter’s value becomes 0000
16
can be set by use of the timer B2 counter (034D
16
) for setting the
frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting
≠
0).
Setting “1” in the effective interrupt output specification bit (bit 1 at 0348
16
) provides the means to choose
which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to
occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0348
16
).
An example of U phase waveform is shown in Figure 1.15.6, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 034A
16
). And set “0” in DUB0 (bit 1 at 034A
16
). In
addition, set “0” in DU1 (bit 0 at 034B
16
) and set “1” in DUB1 (bit 1 at 034B
16
). Also, set “0” in the effective
interrupt output specification bit (bit 1 at 0348
16
) to set a value in the timer B2 interrupt occurrence
frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content
becomes 0000
16
as many as (setting) times. Furthermore, set “1” in the effective interrupt output specifi-
cation bit (bit 1 at 0348
16
), set “0” in the effective interrupt output polarity select bit (bit 0 at 0348
16
) and set
"1" in the interrupt occurrence frequency set counter (034D
16
). These settings cause a timer B2 interrupt
to occur every other interval when the U phase output goes to “H”.
When the timer B2 counter’s content becomes 0000
16
, timer A4 starts outputting one-shot pulses. In this
instance, the content of DU1 (bit 0 at 034B
16
) and that of DU0 (bit 0 at 034A
16
) are set in the three-phase
output shift register (U phase), the content of DUB1 (bit 1 at 034B
16
) and that of DUB0 (bit 1 at 034A
16
)
___
are set in the three-phase output shift register (U phase). After triangular wave modulation mode is se-
lected, however, no setting is made in the shift register even though the timer B2 counter’s content
becomes 0000
16
.
___
The value of DU0 and that of DUB0 are output to the U terminal (P8
0
) and to the U terminal (P8
1
)
respectively. When the timer A4 counter counts the value written to timer A4 (038F
16
, 038E
16
) and when
timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-
___
tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output
signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for
___
setting the time over which the “L” level of the U phase waveform does not lap over the “L” level of the U
phase waveform, which has the opposite phase of the former. The U phase waveform output that started
from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses
even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the
one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already
shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L"
level. When the timer B2 counter’s content becomes 0000
16
, the timer A4 counter starts counting the
value written to timer A4-1 (0347
16
, 0346
16
), and starts outputting one-shot pulses. When timer A4 fin-
ishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the
three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level
changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot
pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the
__
__
three-phase output shift register on the U phase side is used, the workings in generating a U phase
waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
99
RENESAS [ RENESAS TECHNOLOGY CORP ]
