Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
System clock generation circuit
A/D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Timer (16 bits)
On-chip oscillator
UART or
Clock synchronous serial I/O
(3 channels)
Output (timer A): 5
Input (timer B): 6
Clock synchronous serial I/O
(8 bits ✕ 1 channel)
CRC calculation circuit (CCITT)
(Polynomial: X16+X12+X5+1)
CAN module
(1 channel)
Three-phase motor
control circuit
Watchdog timer
(15 bits)
M16C/60 Series CPU core
Memory
R0H
R1H
R0L
R1L
SB
USP
ISP
ROM (1)
RAM (2)
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
Multiplier
D/A converter
(8 bits ✕ 2 channels)
FB
NOTES:
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.2.40 Aug 25, 2006 page 3 of 84
REJ03B0004-0240
RENESAS [ RENESAS TECHNOLOGY CORP ]
