M52036SP
Logic Table
Table.1 Decoder Logic Output
Input to pin 6 HD.COMP
HD. COMP. (POS)
HD. COMP. (POS)
HD. COMP. (POS)
HD. COMP. (NEG)
HD. COMP. (NEG)
HD. COMP. (NEG)
NON
NON
NON
Input to pin 8 VD
NON
VD (POS)
VD (NEG)
NON
VD (POS)
VD (NEG)
NON
VD (POS)
VD (NEG)
Output pins
1
H
H
H
H
H
H
L
L
L
2
L
H
H
L
H
H
L
H
H
18
L
L
L
H
H
H
L
L
L
19
L
L
H
L
L
H
L
L
H
Table.2 Allowable Amplitude of Input Voltage
Amplitude of input to pin 4
Amplitude of input to pin 6
Amplitude of input to pin 8
Table.3 Output Priority
Input signals (pin)
4 pin
6 pin
Ο
Ο
Ο
Ο
×
×
×
×
×
Ο
×
Ο
×
Ο
×
Ο
8 pin
×
×
Ο
Ο
×
×
Ο
Ο
Output signals (pin)
13 pin
14 pin
15 pin
4
11
6
11
4
8
6
8
×
×
6
11
×
8
6
8
17 pin
4
6
4
6
×
6
×
6
Rev.1.0, Sep.22.2003, page 7 of 13
RENESAS [ RENESAS TECHNOLOGY CORP ]
