Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~16
tsu (A)
trec (W)
tsu (S1)
S1
S2
(Note 5)
(Note 5)
(Note 5)
(Note 7)
W
(Note 6)
(Note 5)
th (D)
tsu (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~16
S1
(Note 5)
(Note 5)
tsu (A)
tsu (S2)
trec (W)
S2
W
(Note 7)
(Note 6)
(Note 5)
(Note 5)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 5: Hatching indicates the state is "don't care".
6: Writing is executed while S2 high overlaps S1 and W low.
7: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
8: Don't apply inverted phase signal externally when DQ pin is output mode.
6
RENESAS [ RENESAS TECHNOLOGY CORP ]
