TRC104 参数 Datasheet PDF下载

3 Architecture

The TRC104 is a single-chip FSK transceiver that operates in the worldwide 2.4 GHz ISM band. The TRC104’s

highly integrated architecture requires a minimum of external components. Advanced features including the

TX/RX FIFO and the burst packet data mode significantly reduce the TRC104’s load on the host microcontroller.

As shown in Figure 2, the TRC104 utilizes a dual-conversion superheterodyne receiver architecture with an

image-reject second mixer. The VCO operates directly at the output frequency when transmitting, and is

modulated by a Gaussian-filtered bit stream.

T R C 1 0 4 B lo c k D ia g r a m

V D D R F

P o w e r

A m p

R e g u la to r

A n ti-

a lia s in g

F ilte r

D A C

G a u s s ia n

L o w -p a s s

F ilte r

T X D a ta

T X C lo c k

A m p litu d e C o n tr o l

T X

S w itc h

R F +

R F -

P o w e r

A m p

V C O

P L L

L o o p

F ilte r

C h a rg e

P u m p

P h a s e

F re q u e n c y

D e te c to r

R e f F re q u e n c y

P M O D E

M O D E

C S

S C L K

C lo c k ,

C o n tr o l,

C o n fig

R e g is te r s

a n d F IF O

F r e q u e n c y S e le c t

S D A T

IN T

R S S ID

R S S IA

X T L IN

X T L O U T

D iv id e

b y 8

D iv id e

b y N

R S S I

S u m m e r

R S S I

R X L O 2 -I

R X L O 1

R e c e iv e r

B a n d -p a s s

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L N A

R X L O 2 -Q

C o m p le x

IF F ilte r

IF A m p /L im ite r

F S K

D e te c to r

D a ta &

C lo c k

R e c o v e ry

C lo c k

D a ta

Figure 2

3.1 RF Port

The TRC104 has a differential RF port that is capable of delivering the required transmitter output power at low

supply voltages. The differential RF port also provides common mode signal rejection to enhance receiver

interference immunity. A simple L-C balun can be used to convert the differential port to a single-ended output to

drive an unbalanced antenna, as shown in Figure 3.

3.2 Transmitter Power Amplifier

The power amplifier controls the output power level of the transmitter. The power amplifier has four programmable

power levels. The power level is set by the

PWR

bits in configuration register 0x01.

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Page 8 of 33

TRC104 - 08/13/09