Preliminary
RT8101/A
Figure 7 shows theDC-DC converter's gain vs. frequency.
T
S
The compensation gain uses external impedance networks
ZC and ZF to provide a stable, high bandwidth loop. High
crossover frequency is desirable for fast transient
response, but it often jeopardizes the system stability. In
order to cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency. In the experience,
place the zero at 75% LC filter resonant frequency.
Crossover frequency should be higher than the ESR zero
but less than 1/5 of the switching frequency. The second
pole is placed at half of the switching frequency.
V
V
T
ON
T
OFF
g1
g2
V
- V
OUT
IN
V
L
- V
OUT
I
L
I = I
L
OUT
8080
ΔI
L
Loop Gain
60
4040
Compensation
I
S1
Gain
20
0
0
Modulator
Gain
-20
I
S2
-40
-40
-60
10Hz
10
-60
100Hz
1.0KHz
10KHz
100KHz
100k
1.0MHz
1M
100
1k
10k
vdb(vo) vdb(comp2) vdb(lo)
Frequency
Frequency (Hz)
Figure 7. Bode Plot
Figure 8. The waveforms of synchronous step-down
converter
Component Selection
1) Inductor Selection
According to Figure 8 the ripple current of inductor can be
calculated as follows :
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of the output current
is appropriate. Figure 8 shows the typical topology of
synchronous step-down converter and its related
waveforms.
ΔI
Δt
V
OUT
V
IN
L
D
fs
V
IN
− V
= L
; Δt = ; D =
OUT
V
OUT
(1)
L = (V − V
)×
IN
OUT
V
IN
× fs× ΔI
L
Where :
VIN = Maximum input voltage
VOUT = Output Voltage
Δt = S1 turn on time
i
I
S1
L
L
+
-
V
L
I
i
OUT
C
ΔIL = Inductor current ripple
fS = Switching frequency
D = Duty Cycle
i
S2
+
S1
V
+
r
OR
-
C
V
R
V
S2
IN
L
OUT
+
V
-
C
OC
-
OUT
rC = Equivalent series resistor of output capacitor
www.richtek.com
11
DS8101/A-01 March 2007
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
