R2023K/T
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
60sec. as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For
example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.
• Control Register 2 (Address Fh)
D7
VDSL
VDSL
0
D6
VDET
VDET
0
D5
D4
PON
PON
1
D3
D2
CTFG
CTFG
0
D1
WAFG
WAFG
0
D0
DAFG
DAFG
0
(For Writing)
(For Reading)
Default Settings *)
XST
CLEN1
CLEN1
0
XST
Indefinite
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL
Description
0
Selecting the VDD supply voltage monitoring threshold setting of
(Default)
1.6v.
1
Selecting the VDD supply voltage monitoring threshold setting of
1.3v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET
Description
Indicating supply voltage above the supply voltage monitoring
threshold settings.
0
(Default)
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold
the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring
circuit. Conversely, setting the VDET bit to 1 causes no event.
XST
(3)
Oscillation Halt Sensing Monitor Bit
Description
Sensing a halt of oscillation
XST
0
1
Sensing a normal condition of oscillation
XST
XST
bit will be set to 0 when the oscillation
The
halt
accepts the reading and writing of 0 and 1. The
XST
sensing. The
bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
Description
0
1
Normal condition
Detecting VDD power-on -reset
(Default)
The PON bit is for sensing power-on reset condition.
* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even
after power-on.
* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
XST
INTR
pin stops outputting.
Register 1, and Control Register 2, except
and PON. As a result,
* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
14
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
