s
TIMING CHART
Release Voltage +V
DET
Supply Voltage Detector Threshold -V
DET
(V
DD
)
Minimum Operating Voltage
V
SS
Detector Threshold
Hysteresis
Output Voltage
(OUT)
V
SS
t
PLH
s
DEFINITION OF OUTPUT DELAY TIME
Output Delay Time t
PLH
is defined as follows:
1. In the case of Nch Open Drain Output:
Under the condition of the output pin (OUT) is pulled up through a resistor of 470kΩ to 5V, the time interval between the
rising edge of V
DD
pulse from 0.7V to (+V
DET
)+ 2.0V and becoming of the output voltage to 2.5V.
2. In the case of CMOS Output:
The time interval between the rising edge of V
DD
pulse from 0.7V to (+V
DET
)+ 2.0V and becoming of the output voltage to
(V
DD
/
2) V.
+V
DET
+ 2.0V
Input Voltage
(V
DD
)
0.7V
GND
5.0V
Output Voltage
2.5V
+V
DET
+ 2.0V
Input Voltage
(V
DD
)
0.7V
GND
+V
DET
+2.0V
Output Voltage
+V
DET
+2.0V
2
GND
t
PHL
t
PLH
GND
t
PHL
t
PLH
Nch Open Drain Output
CMOS Output
Rev.1.10
-2-
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
