R
×
5C348A/B
5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function
The R
×
5C348A/B incorporate an oscillation halt sensing circuit equipped with internal registers configured to
record any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up.
As such, the oscillation halt sensing circuit is useful for judging the validity of time data.
The R
×
5C348A/B also incorporate a supply voltage monitoring circuit equipped with internal registers configured
to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings
can be selected between 2.1 and 1.6 volts through internal register settings.
The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to
the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply
voltage monitoring circuit can be applied to battery supply voltage monitoring.
6. Periodic Interrupt Function
The R
×
5C348A/B incorporate a periodic interrupt circuit configured to generate periodic interrupt signals aside
from interrupt signals generated by the alarm circuit for output from the INTR pin. Periodic interrupt signals have
five selectable frequency settings of 2Hz (once per 0.5 seconds), 1Hz (once per 1 second), 1/60Hz (once per 1
minute), 1/3600Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt
signals also have two selectable waveforms of a normal pulse form (with a frequency of 2Hz or 1Hz) and special
form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts).
The register records of periodic interrupt signals can be monitored by using a polling function.
7. 32-kHz Clock Output Function
The R
×
5C348A/B incorporate a 32-kHz clock circuit configured to generate clock pulses with the oscillation
frequency of a 32.768-kHz crystal oscillator for output from the 32KOUT pin (Nch. open drain output). For the
R
×
5C348A, the 32-kHz clock output can be disabled by certain register settings. But it cannot be disabled without
manipulation of any two registers with different addresses, to prevent disabling in such events as the runaway of the
the R
×
5C348A and the R
×
5C348B alike, the 32-kHz clock circuit is enabled at power-on.
CPU. For the R
×
5C348B, however, the 32-kHz clock circuit cannot be disabled by any register settings. For both
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RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
