TABLE 5
TABLE 5
FINAL
FINAL
© 2013 Rochester Electronics, LLC. All Rights Reserved 03112013
79C940
Am79C940
Am79C940
MediaMedia Access Controller for Ethernet (MACE™)
Access Controller for Ethernet (MACE™)
DISTINCTIVE CHARACTERISTICS
DISTINCTIVE CHARACTERISTICS
Integrated Controller with Manchester
Integrated Controller with Manchester
encoder/decoder and 10BASE-T transceiver
encoder/decoder and 10BASE-T transceiver
and AUIand AUI port
port
Arbitrary byte alignment and little/biglittle/big endian
Arbitrary byte alignment and endian
memorymemory interface supported
interface supported
Internal/external loopback capabilities
Internal/external loopback capabilities
Supports IEEE 802.3/ANSI 8802-3 and Ethernet
Supports IEEE 802.3/ANSI 8802-3 and Ethernet External Address Detection Interface (EADI
)(EADI
)
External Address Detection Interface
standards
standards
for externalexternal hardware address filtering in
for hardware address filtering in
84-pin PLCC and 100-pin 100-pin PQFP Packages
84-pin PLCC and PQFP Packages
bridge/router applications
bridge/router applications
80-pin Thin Quad Flat Pack (TQFP) package
80-pin Thin Quad Flat Pack (TQFP) package
JTAG Boundary Scan (IEEE 1149.1) test access access
JTAG Boundary Scan (IEEE 1149.1) test
available for space critical applications such assuch as port interface for board level production test
available for space critical applications
port interface for board level production test
PCMCIA
PCMCIA
Integrated Manchester Encoder/Decoder
Integrated Manchester Encoder/Decoder
ModularModular architectureeasy tuning to
architecture allows allows easy tuning to
Digital Attachment Interface (DAI
) allows ) allows
Digital Attachment Interface (DAI
specificspecific applications
applications
by-passing of differential Attachment Unit
by-passing of differential Attachment Unit
High speed, 16-bit synchronous host system system
High speed, 16-bit synchronous host
interface with 2 or 3 cycles/transfer
interface with 2 or 3 cycles/transfer
Interface (AUI) (AUI)
Interface
Supports the following types oftypes of network
Supports the following network
Individual transmit (136 byte) and receive receive (128 interface:
Individual transmit (136 byte) and (128
interface:
byte) FlFOs provide provide increase of latency latency
— AUI to external external 10BASE2, 10BASE5 or
byte) FlFOs increase of system system
— AUI to 10BASE2, 10BASE5 or
and supportsupport the following features:
and the following features:
10BASE-F MAU MAU
10BASE-F
— Automatic retransmission with no FIFO no FIFO
— Automatic retransmission with
reload reload
— DAI port to external external 10BASE2, 10BASE5,
— DAI port to 10BASE2, 10BASE5,
10BASE-T, 10BASE-F MAU MAU
10BASE-T, 10BASE-F
— General General Purpose Serial Interfaceto
— Purpose Serial Interface (GPSI) (GPSI) to
external external encoding/decoding scheme
encoding/decoding scheme
— Internal 10BASE-T transceiver with
— Internal 10BASE-T transceiver with
automatic selection of 10BASE-T or AUI port AUI port
automatic selection of 10BASE-T or
Sleep mode allows reducedreducedconsump-
Sleep mode allows power power consump-
tion for tion for battery powered applications
critical critical battery powered applications
5 MHz-25 MHz-25 MHz system clock speed
5 MHz system clock speed
SupportSupport for operation in industrial temperature
for operation in industrial temperature
range (–40
°
C to +85
°
C) available in all threeall three
range (–40
°
C to +85
°
C) available in
packages
packages
— Automatic receive strippingstripping and transmit
— Automatic receive and transmit
padding padding (individually programmable)
(individually programmable)
— Automatic runt packet rejectionrejection
— Automatic runt packet
— Automatic deletion deletion of collision frames
— Automatic of collision frames
— Automatic retransmission with no FIFO no FIFO
— Automatic retransmission with
reload reload
Direct slave access to all onto all on board
Direct slave access board
configuration/status registers and transmit/
configuration/status registers and transmit/
receive receive FlFOs
FlFOs
Direct FIFO read/write access for simple simple
Direct FIFO read/write access for
interface to DMA to DMA controllers or l/O processors
interface controllers or l/O processors
GENERAL DESCRIPTION
GENERAL DESCRIPTION
The Media Access Controller for EthernetEthernet (MACE) chip MACE device isdevice isregister based peripheral.
The Media Access Controller for (MACE) chip
The
The MACE a slave a slave register based peripheral.
is a CMOSaVLSI device designed to provide flexibilityflexibility transfers to and from thefrom the are performed
is CMOS VLSI device designed to provide
All
All transfers to and system system are performed
in customized LAN design. The MACE device isdevice is specif- simple memory memory or I/O read and write commands.
in customized LAN design. The MACE specif-
ordering
using simple or I/O read and
page 3
For complete Rochester
using
guide, please refer to
write commands.
ically designed to address address applications where multipleconjunction with a user defined defined DMA engine, the
ically designed to applications where multiple
In
In conjunction with a user DMA
Please consult factory for specific package availability
engine, the
I/O peripherals are present, present, and a centralized or sys-
I/O peripherals are and a centralized or sys-
MACE chip providesprovides an IEEE 802.3 interface tailored
MACE chip an IEEE 802.3 interface tailored
tem specific DMA is required. The high speed, 16-bit 16-bita specific application. Its superior superior modular architec-
tem specific DMA is required. The high speed,
to
to a specific application. Its modular architec-
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
synchronous system
minimum or maximum ratings
optimized for
product characterization, design, simulation, or sample testing.
allow the MACE MACE
synchronousinterfaceinterface is
may be based on
an exter- andture and versatile interface
Rochester Electronics reserves
system is optimized for an exter-
ture
versatile system system interface allow the
only. Certain
nal DMA or DMA
to
or I/O processor
further notice
similar to
nal
the right
processor system, system,
to any specification herein.
I/O
make changes without
and is and is similardevice to be configured as a stand-alone device or
to
device to be configured as a stand-alone device or
many existing existing peripheral devices, such as SCSI and a connectivity cell incorporated into a larger, larger,
many peripheral devices, such as SCSI and
as
as a connectivity cell incorporated into a
serial link controllers.
serial link controllers.
integrated system. system.
integrated
Specification Number 79C940B-CI (A) Rev C
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E
Amendment/0
16235
Rev:
E
Amendment/0
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