TABLE 5
AC CHARACTERISTICS (continued)
No.
17
18
19
20
21
22
23
24
25
26
GPSI Timing
70
71
72
73
74
75
76
77
78
79
80
81
85
86
87
88
89
90
91
t
TXEND
t
TXENH
t
TXDD
t
TXDH
t
RXDR
t
RXDF
t
RXDH
t
RXDS
t
CRSL
t
CLSHI
t
TXH
t
CRSH
t
DSFBDR
t
DSFBDF
t
EAMRIS
t
EAMS
t
EAMR
L
t
SFBDHIH
t
EARS
STDCLK↑ delay to TXEN↑
TXEN hold time from STDCLK↑
TXDAT+ hold time from STDCLK↑
RXDAT rise time
RXDAT fall time
RXDAT hold time (SRDCLK↑ to
RXDAT change)
RXDAT setup time (RXDAT stable
to SRDCLK↑)
RXCRS low time
CLSN high time
TXEN or TXDAT± hold time from
CLSN↑
RXCRS hold time from SRDCLK↑
SRDCLK↓ delay to SF/BD↑
SRDCLK↓ delay to SF/BD↑
EAM/R invalid setup prior to
SRDCLK↓ after SFD
Parameter
Symbol
t
STDC
t
STDCL
t
STDCH
t
STDCR
t
STDCF
t
SRDC
t
SRDCH
t
SRDCL
t
SRDCR
t
SRDCF
Parameter Description
STDCLK period
STDCLK low pulse width
STDCLK high pulse width
STDCLK rise time
STDCLK fall time
SRDCLK period
SRDCLK HIGH pulse width
SRDCLK LOW pulse width
SRDCLK rise time
SRDCLK fall time
79C940
Test Conditions
Min (ns)
99
Max (ns)
101
GPSI Clock Timing
See Note 1
See Note 1
See Note 1
85
38
38
See Note 1
See Note 1
(C
L
= 50 pF)
(C
L
= 50 pF)
(C
L
= 50 pF)
See Note 1
See Note 1
25
0
t
STDC
+ 20
t
STDC
+ 30
32*t
STDC
0
20
20
–150
0
200
100
0
96*t
STDC
5
70
5
8
8
5
5
70
45
45
5
5
115
STDCLK↑ delay to TXDAT+ change (C
L
= 50 pF)
EADI Feature Timing
EAM setup to SRDCLK↓ at bit 6 of
Source Address byte 1 (match
packet)
EAM/R low time
SF/BD high hold from last
SRDCLK↓
EAR setup SRDCLK↓ at bit 6 of
message byte 64
(reject normal packet)
Note:
1. Not tested but data available upon request.
Specification Number 79C940B-CI (A) Rev C
Page 12 of 13
ROCHESTER [ Rochester Electronics ]
