EP610
AC Operating Conditions: EP610-XX/B
Symbol
t
PD1
t
PD2
t
PZX
t
PXZ
t
CLR
f
MAX
t
SU
t
H
t
CH
t
CL
t
CO1
t
CNT
f
CNT
t
ASU
t
AH
t
ACH
t
ACL
t
ACO1
t
ACNT
f
ACNT
Note (1)
Parameter
Input to non-registered output
I/O input to non-registered output
Input to output enable
Input to output disable
Asynchronous output clear time
Maximum clock frequency
Global clock input setup time
Global clock input hold time
Global clock high time
Global clock low time
Global clock to output delay
Global clock minimum period
Global clock internal maximum frequency
Array clock input setup time
Array clock input hold time
Array clock high time
Array clock low time
Array clock to output delay
Array clock minimum period
Array clock internal maximum frequency
C1 = 5 pF
Conditions
C1 = 35 pF
Notes (2), (3)
Min
Max
35
37
35
35
37
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
Notes (2), (3), (4), (5)
Notes (2), (3)
37.0
27
0
12
12
C1 = 35 pF
Note (2), (6), (7)
Note (2), (3)
Note (3)
Note (4)
Note (4)
Note (4), (8)
Note (8)
Notes (2), (3), (4)
Notes (2), (3), (4)
Notes (3), (4)
Notes (3), (4)
Notes (2), (3)
Notes (4), (8)
Notes (4), (8)
20
35
28.5
8
12
12
12
37
35
28.6
ns
ns
MHz
ns
ns
ns
ns
ns
ns
MHz
Notes to tables:
(1) Screening and characterization of AC delay parameters are conducted at 10 MHz or less.
Operating conditions: V
CC
= 5 V ± 10%, T
C
= -55° C to 125° C for military use.
(2) All array-dependent delays are specified for an
XOR
pattern. This pattern includes two product terms and two
pure inputs; all other product terms in the macrocell are held low by one EPROM cell. Other patterns may result
in longer delays. Delays for patterns involving only one product term (such as
t
PXZ
) are specified for an
XOR
pattern in which only one pure input switches at a time.
(3) When the Turbo Bit is not set (non-turbo mode), a non-turbo adder of 30 ns (maximum) is added to this
parameter to determine worst-case timing. Parameters may not be tested in non-turbo mode, but are
guaranteed to the limits specified. Devices operating in non-turbo mode require one input or I/O transition to
guarantee that the device will enter the correct power-up state.
(4) These parameters may not be tested, but are guaranteed to the limits specified in the table under “Absolute
Maximum Ratings” on page 3.
(5) Not tested directly, but guaranteed by testing t
PD
.
(6) The
f
MAX
values represent the highest frequency for pipelined data.
(7) Not tested directly, but derived from
t
SU
.
(8) Specified with device programmed as a 16-bit counter with no output loading.
Specification Number EP610-CI (AT) REV -
Page 8 of 9
ROCHESTER [ Rochester Electronics ]
