8XC196KC/8XC196KC20
Table 2. 8XC196KC Memory Map
PROCESS INFORMATION
Description
Address
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliabili-
ty information is available in the Intel Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
External Memory or I/O
0FFFFH
06000H
®
Internal ROM/OTPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
ROM/OTPROM Security Key
203FH
2030H
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H.
(Note 5)
2019H
270942–43
CCB
2018H
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
Figure 3. The 8XC196KC Family Nomenclature
External Memory
1FFDH
0200H
Table 1. Thermal Characteristics
Package
488 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3, 4)
01FFH
0018H
θ
θ
jc
ja
Type
PLCC
QFP
0017H
0000H
35 C/W
°
13 C/W
°
55 C/W
°
16 C/W
°
NOTES:
SQFP
TBD
TBD
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
3
ROCHESTER [ Rochester Electronics ]
