X28HC256
Pinouts
X28HC256
(28 LD CERDIP, FLATPACK, PDIP, SOIC)
TOP VIEW
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
9
10
11
12
13
14
28
27
26
25
24
23
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28HC256
(32 LD PLCC, LCC)
TOP VIEW
V
CC
WE
A
12
A
14
NC
A
13
A
7
X28HC256
(28 LD PGA)
BOTTOM VIEW
I/O I/O
I/O I/O
I/O
1
2
3
5
6
12
13
15
17
18
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
I/O A
0
0
10
11
A
1
9
A
3
7
A
5
5
A
6
4
V
I/O
I/O
SS
4
7
14
16
19
4 3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
2 1 32 31 30
29
28
27
X28HC256
26
25
24
23
22
X28HC256
8
21
20
19
18
17
16
15
A
2
CE A
10
8
20
21
X28HC256
A
4
OE A
11
6
23
22
A
12
V
CC
A
9
2
28
24
A
7
3
1
A
14
A
8
25
12
22
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
WE A
13
27
26
Pin Descriptions
Addresses (A
0
to A
14
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O
0
to I/O
7
)
Data is written to or read from the X28HC256 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
4
FN8108.2
May 7, 2007
ROCHESTER [ Rochester Electronics ]
