K4D263238F
EXTENDED MODE REGISTER SET(EMRS)
128M DDR SDRAM
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The
default value of the extended mode register is not defined, therefore the extend mode register must be written after power
up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high
on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode
register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going
low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-
ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks
are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins
except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
Extended
Mode Register
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
BA
0
0
1
A
n
~ A
0
MRS
EMRS
A
6
0
1
A
1
1
1
Output Driver Impedance Control
Weak
Matched
A
0
0
1
DLL Enable
Enable
Disable
* RFU(Reserved for future use)
should stay "0" during EMRS
cycle.
Figure 7. Extend Mode Register set
- 9 -
Rev 1.1 (May 2003)
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
