K4S281632B
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
CMOS SDRAM
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
Unit
V
V
ns
V
1200Ω
Output
870Ω
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Output
Z0 = 50Ω
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
- 75
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
-
65
68
15
20
20
45
- 80
16
20
20
48
Version
- 1H
20
20
20
50
100
70
2
2 CLK + 20 ns
1
1
1
2
1
70
80
- 1L
20
20
20
50
-10
20
24
24
50
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
1
2,5
5
2
2
3
4
1
1
1
1
Unit
Note
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -80/1H/1L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.0 Aug. 1999
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
