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K4S281632C-TC1L 参数 Datasheet PDF下载

K4S281632C-TC1L图片预览
型号: K4S281632C-TC1L
PDF下载: 下载PDF文件 查看货源
内容描述: 的128Mbit SDRAM 2米x 16Bit的×4银行同步DRAM LVTTL [128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 11 页 / 116 K
品牌: SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
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K4S281632C
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
CAS latency=3
CAS latency=2
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
t
OH
3
-
2.5
2.5
1.5
0.8
1
5.4
-
t
SAC
Symbol
Min
CLK cycle time
t
CC
7.5
-
5.4
-
3
3
3
3
2
1
1
6
6
- 75
Max
1000
Min
10
10
6
6
3
3
3
3
2
1
1
- 1H
Max
1000
Min
10
12
CMOS SDRAM
- 1L
Max
1000
6
7
ns
ns
ns
ns
ns
ns
6
7
ns
2
3
3
3
3
2
ns
1
Unit
Note
ns
1,2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Output fall time
Output rise time
Output fall time
Symbol
trh
tfh
trh
tfh
Condition
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Min
1.37
1.30
2.8
2.0
3.9
2.9
Typ
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Notes :
1. Rise time specification based on 0pF + 50
to V
SS
, use these values to design to.
2. Fall time specification based on 0pF + 50
to V
DD
, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
SS
.
Rev. 0.0 Mar. 2000