K4S641632E
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
CLK cycle
time
CLK to valid
output delay
Output data
hold time
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
t
OH
t
SAC
Symbol
5
-
-
-
2
-
2
2
1.5
1
1
4.5
-
4.5
-
- 50
- 55
- 60
- 70
- 75
CMOS SDRAM
- 1H
- 1L
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t
CC
1000
5.5
-
-
-
2
-
2
2
1.5
1
1
5
-
5
-
2.5
-
2.5
2.5
1.5
1
1
5
-
1000
6
-
5
-
3
-
3
3
2
1
1
6
-
1000
7
-
6
-
3
3
2.5
2.5
1.5
0.8
1
5.4
6
1000
7.5
10
5.4
6
3
3
3
3
2
1
1
6
6
1000
10
10
6
6
3
3
3
3
2
1
1
6
7
ns
ns
ns
ns
ns
ns
3
3
3
3
2
1000
10
12
6
7
ns
2
ns
1,2
1000
ns
1
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output CAS latency=3
in Hi-Z
CAS latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Output rise time
Output fall time
Output rise time
Output fall time
Symbol
trh
tfh
trh
tfh
Condition
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Measure in linear
region : 1.2V ~ 1.8V
Min
1.37
1.30
2.8
2.0
3.9
2.9
Typ
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Notes :
1. Rise time specification based on 0pF + 50
Ω
to V
SS
, use these values to design to.
2. Fall time specification based on 0pF + 50
Ω
to V
DD
, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
SS
.
Rev.0.2 Sept. 2001
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
