K4S643232C
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refresh
Exit
L
H
H
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
CMOS SDRAM
,
A
10
/AP
A
9
~ A
0
Note
H
H
X
H
L
H
X
X
L
L
L
H
L
L
H
X
L
H
L
L
H
X
H
L
L
H
H
X
H
H
X
X
OP code
X
1,2
3
3
X
X
X
V
V
X
Row address
L
H
Column
address
(A
0
~ A
7
)
Column
address
(A
0
~ A
7
)
3
3
Bank active & row addr.
Read &
column address
Write &
column address
Burst Stop
Precharge
Bank selection
All banks
Clock suspend or
active power down
Entry
Exit
Entry
Precharge power down mode
Exit
DQM
No operation command
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
L
4
4,5
4
4,5
6
H
H
H
X
X
X
L
L
L
H
L
H
H
L
X
V
X
X
H
X
V
X
L
H
H
X
V
X
X
H
X
V
L
L
L
X
V
X
X
H
X
V
X
X
X
V
L
H
X
V
X
L
H
X
H
L
H
L
H
L
X
X
X
X
X
X
V
X
X
7
X
H
L
L
H
H
H
H
L
X
H
L
X
H
X
H
X
H
X
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A
0
~ A
10
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If both BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank B is selected.
If both BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
-9-
REV. 1.1 Nov. '99
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
