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K4S643232C-TC80 参数 Datasheet PDF下载

K4S643232C-TC80图片预览
型号: K4S643232C-TC80
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×32 SDRAM 512K X 32位×4银行同步DRAM LVTTL [2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL]
分类和应用: 动态存储器
文件页数/大小: 43 页 / 1151 K
品牌: SAMSUNG [ SAMSUNG ]
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K4S643232C  
CMOS SDRAM  
Version  
-70  
7
Parameter  
Symbol  
Unit  
-55  
5.5  
-60  
6
-80  
8
-10  
10  
CLK cycle time  
tCC(min)  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRCD(min)  
tRP(min)  
11  
12  
18  
18  
42  
14  
16  
20  
20  
48  
20  
20  
20  
48  
16.5  
16.5  
38.5  
21  
Row precharge time  
21  
tRAS(min)  
tRAS(max)  
tRC(min)  
tRFC(min)  
49  
Row active time  
100  
70  
Row cycle time  
55  
66  
60  
72  
70  
70  
70  
70  
Row cycle time in Auto refresh  
70  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket  
code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency.  
6. A new command should be issued after self refersh exit followed by tRFC.  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-55  
-60  
-70  
-80  
-10  
Parameter  
Symbol  
tCC  
Unit Note  
Min Max Min Max Min Max Min Max Min Max  
CAS Latency=3  
5.5  
-
6
7
8
10  
-
10  
12  
-
CLK cycle time  
1000  
1000  
1000  
1000  
1000 ns  
1
CAS Latency=2  
CAS Latency=3  
CAS Latency=2  
-
-
-
-
-
5
-
5.5  
5.5  
6
6
-
6
8
-
CLK to valid  
output delay  
tSAC  
ns  
1, 2  
-
-
-
-
-
-
-
-
-
Output data  
tOH  
tCH  
2
2
-
-
2.5  
2.5  
-
2.5  
2.5  
2.5  
ns  
ns  
2
3
CAS Latency=3  
CAS Latency=2  
CAS Latency=3  
CAS Latency=2  
CAS Latency=3  
CAS Latency=2  
-
CLK high pulse width  
-
-
-
3
3
-
-
-
3
3
2
-
-
-
3.5  
3.5  
2.5  
-
-
-
-
2
-
-
2.5  
-
CLK low pulse width  
Input setup time  
tCL  
tSS  
ns  
ns  
3
3
-
1.5  
-
-
1.5  
-
1.75  
-
-
1
1
-
Input hold time  
tSH  
1
1
-
-
1
1
-
-
-
-
-
1
1
-
-
-
1
1
-
-
-
ns  
ns  
3
2
CLK to output in Low-Z  
tSLZ  
-
CAS Latency=3  
CAS Latency=2  
5
-
5.5  
-
5.5  
-
6
6
6
8
CLK to output  
in Hi-Z  
tSHZ  
ns  
-
-
-
-
-
Note :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
REV. 1.1 Nov. '99  
- 8 -