K6T1008C2E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=4.5~5.5V, Commercial Product: T
A
=0 to 70°C, Industrial Product: T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Read
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
20
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
25
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
V
DR
CS
1
≥Vcc-0.2V
1)
K6T1008C2E-L
Data retention current
I
DR
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
K6T1008C2E-B
K6T1008C2E-P
K6T1008C2F-F
Data retention set-up time
Recovery time
t
SDR
t
RDR
See data retention waveform
Test Condition
Min
2.0
-
-
-
-
0
5
Typ
-
-
-
-
-
-
-
Max
5.5
20
10
25
10
-
-
ms
µA
Unit
V
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
5
Revision 3.0
March 2000
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
