K6X4016C3F Family
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled)
t
WC
Address
t
CW(2)
CS
t
AW
t
BW
t
AS(3)
t
WP(1)
WE
t
DW
Data in
Data Valid
t
DH
t
WR(4)
CMOS SRAM
UB, LB
Data out
NOTES
(WRITE CYCLE)
High-Z
High-Z
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
t
SDR
Data Retention Mode
t
RDR
2.2V
V
DR
CS≥V
CC
- 0.2V
CS
GND
8
Revision 1.0
September 2003
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
