K7I163682B
K7I161882B
Document Title
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Add the speed bin (-33, -30)
2. Delete the speed bin (-25, -13)
1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
1. Add the speed bin (-25)
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.
1. Change the ISB1.
Speed Bin
-30
-25
-20
-16
1.0
2.0
1. Final spec release
1. Delete the x8 Org.
2. Delete the 300MHz speed bin
1. Add the 300MHz speed bin
1. Change the stand-by current(I
SB1
)
before
after
Isb1
-30 :
230
260
-25 :
210
240
-20 :
190
220
-16 :
170
200
From
200
180
160
140
To
230
210
190
170
Oct. 31, 2003
Nov. 28, 2003
Final
Final
Draft Date
Oct. 23. 2002
Oct. 24. 2002
Remark
Advance
Premilinary
0.2
Dec. 16, 2002
Premilinary
0.3
0.4
Jan. 27, 2003
Mar. 20, 2003
Premilinary
Premilinary
0.5
April. 4, 2003
Premilinary
0.6
June. 20, 2003
Premilinary
0.7
Oct. 20. 2003
Premilinary
3.0
3.1
June. 18, 2004
July. 28, 2004
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July. 2004
Rev 3.1
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
