K9F1208U0M-YCB0, K9F1208U0M-YIB0
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0
FLASH MEMORY
History
1. Initial issue
Draft Date
Oct. 27th 2000
Remark
Advanced
Information
0.1
1. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
1. Changed GND input (pin # 6) pin to N.C ( No Connection).
- The pin # 6 is don’t-cared regardless of external logic input level
and is fixed as low internally.
1. Changed plane address in Copy-Back Program
-
A24 and A25
must be the same between source and target page
=>
A14 and A15
must be the same between source and target page
1. Changed DC characteristics
Parameter
Operating
Current
Sequential Read
Program
Erase
Min
-
-
-
Typ
10
10
10
Max
20->30
20->30
20->30
mA
Unit
Dec. 5th 2000
0.2
Dec. 15th 2000
0.3
Jan. 8th 2001
0.4
Apr. 7th 2001
2. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)
Parameter
ALE to RE Delay( ID read )
CE to RE Delay( ID read)
RE Low to Status Output
CE Low to Status Output
RE access time(Read ID)
- AC characteristics (After)
. Deleted t
CR
,t
RSTO,
t
CSTO
and t
READID
/ Added t
CEA
Parameter
ALE to RE Delay( ID read )
CE Access Time
Symbol
t
AR1
t
CEA
Min
10
-
Max
-
45
Unit
ns
Symbol
t
AR1
t
CR
t
RSTO
t
CSTO
t
READID
Min
100
100
-
-
-
Max
-
-
35
45
35
ns
Unit
1
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
