欢迎访问ic37.com |
会员登录 免费注册
发布采购

K9GAG08U0M 参数 Datasheet PDF下载

K9GAG08U0M图片预览
型号: K9GAG08U0M
PDF下载: 下载PDF文件 查看货源
内容描述: [三星2G闪存芯片资料]
分类和应用: 闪存
文件页数/大小: 51 页 / 1361 K
品牌: SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
 浏览型号K9GAG08U0M的Datasheet PDF文件第3页浏览型号K9GAG08U0M的Datasheet PDF文件第4页浏览型号K9GAG08U0M的Datasheet PDF文件第5页浏览型号K9GAG08U0M的Datasheet PDF文件第6页浏览型号K9GAG08U0M的Datasheet PDF文件第8页浏览型号K9GAG08U0M的Datasheet PDF文件第9页浏览型号K9GAG08U0M的Datasheet PDF文件第10页浏览型号K9GAG08U0M的Datasheet PDF文件第11页  
K9GAG08B0M
K9GAG08U0M K9LBG08U1M
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
Pin Function
Preliminary
FLASH MEMORY
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
7