K9GAG08B0M
K9GAG08U0M K9LBG08U1M
Figure 1. K9GAG08X0M Functional Block Diagram
V
CC
V
SS
A
13
- A
31
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
16,384M + 512M Bit
NAND Flash
ARRAY
Preliminary
FLASH MEMORY
A
0
- A
12
(4,096 + 128)Byte x 524,288
Data Register & S/A
Y-Gating
Command
Command
Register
I/O Buffers & Latches
V
CC
V
SS
Output
Driver
I/0 0
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
I/0 7
CLE ALE WP
Figure 2. K9GAG08X0M Array Organization
1 Block = 128 Pages
(512K + 16K) Bytes
512K Pages
(=4,096 Blocks)
8 bit
4K Bytes
128 Bytes
1 Page = (4K + 128)Bytes
1 Block = (4K + 128)B x 128 Pages
= (512K + 16K) Bytes
1 Device = (4K+128)B x 128Pages x 4,096 Blocks
= 16,896 Mbits
Page Register
4K Bytes
I/O 0
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A
0
A
8
A
13
A
21
A
29
I/O 1
A
1
A
9
A
14
A
22
A
30
I/O 2
A
2
A
10
A
15
A
23
A
31
128 Bytes
I/O 3
A
3
A
11
A
16
A
24
*L
I/O 0 ~ I/O 7
I/O 4
A
4
A
12
A
17
A
25
*L
I/O 5
A
5
*L
A
18
A
26
*L
I/O 6
A
6
*L
A
19
A
27
*L
I/O 7
A
7
*L
A
20
A
28
*L
Column Address
Column Address
Row Address
Row Address
Row Address
NOTE
: Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
8
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
