PRELIMINARY
KM681000C Family
Document Title
128K x8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
0.1
History
Initial draft
First revision
- Seperate read and write at I
CC
, I
CC1
I
CC =
I
CC1
→
Read : 15mA, Write : 35mA
Finalized
- Add 70ns speed bin for commercial product and 85ns speed
bin for industrial.
Revised
- Improved operating current
Add typical value.
I
CC
Read : 15mA
→
10mA(Remove write current)
I
CC2
: 90mA
→
60mA
- Speed bin change
Remove 45ns from commercial part
Remove 55ns and 100ns from industrial part.
Draft Date
November 22, 1995
April 15, 1996
Remark
Design target
Preliminary
1.0
September 5, 1996
Final
2.0
November 5, 1997
Final
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
November 1997