PRELIMINARY
KM681002B, KM681002BI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width( OE High)
Write Pulse Width( OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM681002B-8
Min
8
6
0
6
6
8
0
0
4
0
3
Max
-
-
-
-
-
-
-
4
-
-
-
KM681002B-10
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
KM681002B-12
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary
PRELIMINARY
CMOS SRAM
NOTE: The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address
t
OH
Data Out
Previous Valid Data
t
AA
Valid Data
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
RC
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO
t
OE
OE
t
OLZ
Data out
V
CC
Current
I
CC
I
SB
t
LZ(4,5)
Valid Data
t
PU
50%
t
PD
50%
t
OH
t
HZ(3,4,5)
CS
t
OHZ
-5-
Rev 2.0
February 1998
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
