KS8620
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
Symbol
V
BB
GND
A
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/
CLKSEL
1 Chip CODEC for Digital Answering phone
Description
V
BB
= -5V
+
5%
Analog ground
Analog output of the receiver filter
Vcc = +5V
+
5%
Receive frame sync pulse. 8KHz pulse train.
PCM data input
Logic input which selects either 1.536MHz / 1.544MHz or 2.048MHz for master
clock in normal operation and BCLKx is used for both TX and RX directions.
Alternately direct clock input available, vary from 64KHz to 2.048MHz.
8
MCLK
R
/
PDN
When MCLK
R
is connected continuously high, the device goes powered down .
Normally connected continuously low, MCLKx is selected for all DAC timing.
Alternately direct 1.536MHz / 1.544MHz or 2.048MHz clock input is available.
9
10
MCLK
X
BCLK
X
D
X
FS
X
TS
X
GS
X
VF
X
I-
VF
X
I+
1.536MHz / 1.544MHz or 2.048MHz clock input is available
May be vary from 64KHz 2.048MHz, but BCLKx is externally tied with MCLKx
in normal operation.
11
12
13
14
PCM data output.
TX frame sync pulse. 8KHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier.
Used to set gain through external resistor between pin 14 to pin 15.
15
16
Inverting input stage of the TX analog signal.
Non-inverting input stage of the TX analog signal.
ABSOLUTE MAXIMUM RATINGS ( Ta = 25
o
C)
Characteristic
Positive Supply Voltage
Negative Supply Voltage
Voltage at any Analog Input or Output
Voltage at any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range ( soldering , 10 sec )
Symbol
Vcc
V
BB
V
I (A)
V
I (D)
Ta
T
STG
T
LEAD
Value
+7
-7
Vcc + 0.3 to VBB - 0.3
Vcc + 0.3 to GNDA - 0.3
0 to 70
-65 to +150
300
Unit
V
V
V
V
o
C
o
C
o
C
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
