LC36256AL, AML-70/85/10/12
• Write Cycle (2): CE Control
Note (6)
Notes
(1) t
COD
, t
OOD
, and t
WOD
are defined as the time at which the outputs becomes the high impedance state and
are not referred to output voltage levels.
(2) An external antiphase signal must not be applied when D
OUT
is in the output state.
(3) t
WP
is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE
to the rising of CE or WE whichever is earlier.
(4) t
CW
is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to
the rising of CE or WE whichever is earlier.
(5) D
OUT
goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level.
(6) When OE is high-level during the write cycle, D
OUT
goes to the high-impedance state.
Data Retention Characteristics
at Ta = 0 to +70°C
Parameter
Data retention supply voltage
Symbol
V
DR
I
CCDR1
Data retention supply current
I
CCDR2
CE setup time
CE hold time
t
CDR
t
R
** t
RC
= Read Cycle time
Conditions
V
CE
≥
V
CC
–0.2V
V
CC
= 3.0V,
V
CE
≥
2.8V
V
CC
= 2.0 to 5.5V,
V
CE
≥
V
CC
–0.2V
0
t
RC**
0.5
25
µA
ns
ns
0 to +70°C
0 to +40°C
25°C
0.25
min
2.0
typ*
max
5.5
10
2
1
µA
Unit
V
* Reference values at V
CC
= 5V, Ta = 25°C
Data Retention Waveform
No. 4163-6/7
SANYO [ SANYO SEMICON DEVICE ]
