LC78622NE
Continued from preceding page.
Output pin states
during a reset
Pin No.
Symbol
I/O
Function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SBCK
FSX
I
O
O
I
Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.)
Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
Subcode Q output standby output
—
Undefined
WRQ
RWC
SQOUT
COIN
CQCK
RES
Undefined
Read/write control input. This is a Schmitt input.
—
O
I
Subcode Q output
Undefined
Command input from the control microprocessor
—
I
Input for both the command input clock and the subcode readout clock. This is a Schmitt input.
Chip reset input. This pin must be set low briefly after power is first applied.
Test output. Leave open. (Normally outputs a low level.)
16.9344 MHz output.
—
I
—
Low-level output
Clock output
Clock output
—
TST11
16M
O
O
O
I
4.2M
4.2336 MHz output
TEST5
CS
Test input. A pull-down resistor is built in. Must be connected to 0 V.
Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled.
Test input. No pull-down resistor. Must be connected to 0 V.
I
—
TEST1
I
—
Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDD, LVDD, RVDD, and XVDD
.
Pin Applications
+
1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV
An EFM signal (NRZ) sliced at an optimal level can be acquired
by inputting the HF signal to EFMIN.
The LC78622NE handles defects as follows. When a high level
is input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice
level control outputs) go to the high-impedance state, and the
slice level is held. However, note that this function is only valid
in CLV phase control mode, that is, when the V/P pin (pin 14) is
low. This function can be used in combination with the
LA9240M and LA9241M DEF pins.
+
Note: If the EFMIN and CLV signal lines are too close to each
other, unwanted radiation can result in error rate
degradation. We recommend laying a ground or V
shield line between these two lines.
DD
2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
Since the LC78622NE includes a VCO circuit, a PLL circuit
can be formed by connecting an external RC circuit. ISET is the
charge pump reference current, PDO is the VCO circuit loop
filter, and FR is a resistor that determines the VCO frequency
range.
(Reference values)
R1 = 68 kΩ, C1 = 0.1 µF
R2 = 680 Ω, C2 = 0.1 µF
R3 = 1.2 kΩ
No. 6015-8/31
SANYO [ SANYO SEMICON DEVICE ]
