Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circuit Description (continued)
DAC Voltage Output Overview
Minimum / Maximum Output Voltages
The output voltage of Group A, B, C, and D DACs is
governed by the following equation:
See Table 2 for the minimum and maximum possible
voltages of a voltage output.
R_GAIN_[A:D]
R_MASTER
DATA
8192
=
K
* V
REF
V
V
OFFSET_[A:D]
*
+
*
G[A:D]
OUT_[A:D]
DAC Setting
VOUT_[A:D] (V)
MSB ... LSB
Equation 1.
0000H
1FFFH
V
OFFSET_[A:D]
where:
V
DATA corresponds to the base-10 value of the binary data
loaded into the shift register shown in Figure 2.
MAX_[A:D]
K
is a multiplying factor that is fixed, as follows:
G[A:D]
Table 2. Minimum/Maximum Output Voltages
K
= 4
= 8
K
= 4
= 4
GA
GB
K
K
where:
GC
GD
V
= 2.5V
V
is defined in equation 2
and
OFFSET[A:D]
REF
Offset
R_GAIN_[A:D]
R_MASTER
8191
8192
K
* V
=
*
V
*
V
+
The offset for each of the voltage DACs is governed by the
following equation:
G[A:D]
REF
MAX_[A:D]
OFFSET_[A:D]
R_OFFSET_[A:D]
0.5 –
V
V
REF
K
*
*
Equation 3.
=
OFFSET_[A:D]
OFFSET
R_MASTER
Equation 2.
The most negative voltage possible for the Edge6420 is
where:
–3.5V when VEE = –4.5V.
K
= 2
Resolution
OFFSET
V
= 2.5V
The resolution of the DACs in Groups A, B, C, and D is:
13
REF
V
/ 2
RANGE_[A:D]
External Resistors
where V
is defined in Equation 4.
RANGE_[A:D]
The recommended resistor values for the above equations
are as follows:
Range
R_MASTER = 100KΩ (0.1% precision)
The range of the DACs in Groups A, B, C and D is:
R_GAIN_[A:D] = (0.4 to 1.15) * R_MASTER
R_OFFSET_[A:D] = (0.0 to 1.2) * R_MASTER
R_GAIN_[A:D]
R_MASTER
8191
8192
K
V
V
=
G[A:D]
REF
*
RANGE_[A:D]
*
*
Equation 4.
2000 Semtech Corp.
7
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