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LCDA05.TB 参数 Datasheet PDF下载

LCDA05.TB图片预览
型号: LCDA05.TB
PDF下载: 下载PDF文件 查看货源
内容描述: 低电容TVS二极管阵列高速数据接口 [Low Capacitance TVS Diode Array For High-Speed Data Interfaces]
分类和应用: 瞬态抑制器二极管电视光电二极管局域网
文件页数/大小: 8 页 / 165 K
品牌: SEMTECH [ SEMTECH CORPORATION ]
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Low Capacitance TVS Diode Array
For High-Speed Data Interfaces
PROTECTION PRODUCTS
Description
The LCDA series of TVS arrays are designed to protect
sensitive electronics from damage or latch-up due to
ESD and other voltage-induced transient events. Each
device will protect two high-speed lines. They are
available with operating voltages of 5V, 12V, 15V and
24V. They are bidirectional devices and may be used on
lines where the signal polarities are above and below
ground.
TVS diodes are solid-state devices designed specifically
for transient suppression. They offer desirable charac-
teristics for board level protection including fast re-
sponse time, low operating and clamping voltage and
no device degradation. The LCDA series devices
feature low capacitance compensation diodes in series
with standard TVS diodes to provide an integrated, low
capacitance solution for use on high-speed interfaces.
The LCDA series devices may be used to meet the
immunity requirements of IEC 61000-4-2, level 4.
LCDA05 through LCDA24
Features
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (lightning) (8/20µs)*
Protects two I/O lines
Low capacitance for high-speed data lines
Working voltages: 5V, 12V, 15V and 24V
Low leakage current
Low operating and clamping voltages
Solid-state silicon avalanche technology
Mechanical Characteristics
JEDEC SO-8 package
Molding compound flammability rating: UL 94V-0
Marking : Part Number, Date Code
Packaging : Tape and Reel per EIA 481
Applications
High-Speed Data Lines
Microprocessor Based Equipment
Universal Serial Bus (USB) Port Protection
Notebooks, Desktops, and Servers
Instrumentation
LAN/WAN Equipment
Peripherals
*See Electrical Characteristics Tables for Ipp
Circuit Diagram (Each Line Pair)
Schematic & PIN Configuration
Pin 1 and 2
1
8
2
7
3
6
4
5
Pin 7 and 8
SO-8 (Top View)
Revision 08/15/2006
1
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