PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINARY - December 2, 1999
SC1186
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1186 PWM
controller. High currents switching at 140kHz are pre-
sent in the application and their effect on ground plane
voltage differentials must be understood and mini-
mized.
1). The high power parts of the circuit should be laid
out first. A ground plane should be used, the number
and position of ground plane interruptions should be
such as to not unnecessarily compromise ground plane
integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the
input capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high
current, fast transition switching. Connections should
be as wide and as short as possible to minimize loop
inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in
electrically “cleaner” grounds for the rest of the system
and c) minimize source ringing, resulting in more reli-
able gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection
between the output inductor and the sense resistor
should be a wide trace or copper area, there are no
fast voltage or current transitions in this connection
and length is not so important, however adding unnec-
essary impedance will reduce efficiency.
12V IN
5V
10
1
2
3
4
0.1uF
5
6
0.1uF
7
8
9
10
11
12
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
24
23
22
Cin
21
20
19
18
17
16
15
14
13
Q2
Cout
4uH
+
Q1
+
1.00k
5mOhm
Vout
2.32k
SC1186
Heavy lines indicate
3.3V
Q3
+
Cin Lin
Cout Lin1
+
Vo Lin1
high current paths.
Vo Lin2
Q4
+
Cout Lin2
Layout diagram for the SC1186
8
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
SEMTECH [ SEMTECH CORPORATION ]
