SC1189
POWER MANAGEMENT
Component Selection (Cont.)
sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp R
DS(ON)
to allow for temperature rise.
FET type
IRL34025
IRL2203
Si4410
R
DS(on)
(m
Ω)
15
10.5
20
P
D
(W)
1.69
1.19
2.26
Package
D
2
Pak
D
2
Pak
S0-8
CAPACITORS
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra
output capacitance or, more usually, additional input ca-
pacitors. Choosing low ESR input capacitors will help maxi-
mize ripple rating for a given size.
RESIST
GATE RESISTOR SELECTION - The gate resistors for the
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be deter-
mined in the application, with the final layout and FETs.
LIMIT, DROOP
CURRENT SENSE, LIMIT, DR OOP AND OFFSET
The converter is protected and it’s loadline shaped by the
signals generated from the sense resistor and associated
components.
CURRENT LIMIT CIRCUIT
BOTT
TTOM
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
2
P
COND
=
I
O
⋅
R
DS( on)
⋅
(1
− δ
)
For the example above:
FET type
IRL34025
IRL2203
Si4410
R
DS(on)
(m
Ω)
15
10.5
20
P
D
(W)
1.33
0.93
1.77
Package
D
2
Pak
D
2
Pak
S0-8
V
CS
Io
R
D
R
F
R
S
+
Ra
VOSENSE
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40
o
C/W for the D
2
PAK and 80
o
C/W for the
SO-8 are readily achievable. The corresponding tempera-
ture rise is detailed below:
Temperature Rise (
O
C)
FET type
IRL34025
IRL2203
Si4410
Top FET
67.6
47.6
180.8
Bottom FET
53.2
37.2
141.6
Vo
INDUCTOR
Rb
Rc
DROOP
AND
OFFSET
CIRCUIT
Rload
Current Limit, Droop and Offset circuit
Current Limit is given by
I
OLIM
= V
CS
.(R
D
+R
F
)/(R
S
.R
F
)
At no load the output voltage is given by:
V
O
=V
O(nom)
*(1+(Ra.Rb)/(Rc*(Ra+Rb))
so the offset is:
V
OS
=V
O(nom)
*1000*(Ra.Rb)/(Rc*(Ra+Rb))
and the droop is calculated as:
V
D
=Io*R
S
*Rb/(Ra+Rb)
where R
S
is in mΩ, V
OS
and V
D
in mV
For a full design procedure for droop and offset, see Appli-
cation Note AN97-9, “Using Droop and Vout Offset for im-
proved transient response”.
10
www.semtech.com
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
2007 Semtech Corp.
SEMTECH [ SEMTECH CORPORATION ]
