SC4517A
POWER MANAGEMENT
Application Information (Cont.)
Thermal Considerations
There are three major power dissipation sources for the
SC4517A. The internal switch conduction loss, its
switching loss due to the high frequency switching actions
and the base drive boost circuit loss. These losses can
be estimated as:
P
total
=
I
o
⋅
R
on
⋅
D
+
22.5
⋅
10
−
3
⋅
I
o
⋅
V
I
+
2
G
VD
(s)
=
2.5
⋅
R
L
s
1
+
1
R
L
⋅
C
10
⋅
I
o
⋅
D
⋅
( V
boost
)
500
Where:
R
L
– Load and
C – Output capacitor.
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
Where:
I
O
= load current;
R = on-equivalent resistance of the switch;
ON
V
BOOST
= input voltage or output based on the boost circuit
connection.
The junction temperature of the SC4517A can be
further decided by:
T
J
=
T
A
+ θ
JA
⋅
P
total
1
SC4517
SW
FB
3
6
7
θ
JA
is the thermal resistance from junction to ambient.
Its value is a function of the IC package, the application
layout and the air cooling system. It is recommended that
a big copper area attached to Pin 4 or the thermal pad
be used for better cooling condition.
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V
F
).
P
diode
=
V
F
⋅
I
o
⋅
(1
−
D )
L1
IN
EN
SYNC
BST
2
5
8
Vout
R1
C
GND
4
COMP
C4
C5
R3
D2
R2
Figure 3. Compensation network provides 2 poles and 1
zero.
The compensation network gives the following
characteristics:
s
ω
Z
R
2
⋅
g
m
⋅
G
COMP
(s)
= ω
1
⋅
s
R
1
+
R
2
s
⋅
(1
+
)
ω
P 2
1
+
Loop Compensation Design
The SC4517A has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:
V
O
=
1.2
•
(1
+
R
1
)
R
2
Where:
ω
1
=
ω
Z
=
ω
P 2
=
1
C
4
+
C
5
1
R
3
⋅
C
4
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4517A will be as follows:
2006 Semtech Corp.
10
C
4
+
C
5
R
3
⋅
C
4
⋅
C
5
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