SC4905A/B
POWER MANAGEMENT
Application Information (Cont.)
VDD UNDER VOLTAGE LOCK OUT
According to the application, and the voltages available,
the SC4905A (UVLO = 4.4V), or the SC4905B (UVLO =
11.6V) can be used to provide the VDD undervoltage
lock out function to ensure the converters controlled
start up.
Before the VDD UVLO has been reached, the internal ref-
erence, oscillator, OUT driver, and logic are disabled.
REFERENCE
A 4V (SC4905A) or a 5V(SC4905B) reference voltage is
available that can be used to source a typical current
up to 5mA to the external circuitry. The REF can be used
to provide the feed back circuitry with a regulated bias.
OSCILLATOR
The oscillator frequency is set by connecting a RC network
as shown below.
Vin
Since the Rosc is referenced to the input supply voltage,
any variation in the supply is directly translated into a
variation in the duty cycle, while maintaining the fixed
frequency operation.
Following equation can be used to calculate the oscilla-
tor frequency:
F
OSC
VFF
Vin
−
2
≅
(
R
OSC
•
C
OSC
•
VFF
•
1.05
)
The recommended range if timing resistors is between
10 kohm and 500kohm and range of timing capacitors
is between 100pF and 1000pF. Timing resistors less
than 10 kohm should be avoided.
SC4905
U1
RT
280k
Rosc
499k
1
2
3
4
VDD
FB
VFF
DMAX
RC
REF
OUT
GND
ILIM
SYNC
10
9
8
7
6
RM
2k
5
RB
8.25k
Cosc
220p, 16V
The oscillator has a ramp voltage that will track the volt-
age at the VFF pin (1.2V<VFF<3.6V). The oscillator peak
voltage is derived by charging the oscillator capacitor (Cosc)
to the VFF voltage via the oscillator resistor (Rosc). The
bias current to charge the Cosc is controlled by the Rosc.
Once the RC pin has reached the VFF voltage, the oscil-
lator ramp is discharged by an internal switch hence cre-
ating the triangle oscillator ramp.
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8
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