LH5P860
FEATURES
•
65,536
×
8 bit organization
•
Access time: 80 ns (MAX.)
•
Cycle time: 140 ns (MIN.)
•
Single +5 V power supply
•
Pin compatible with 1M standard SRAM
•
Power consumption (MAX.):
Operating: 440 mW
Self refresh (TTL level): 5.5 mW
Self refresh (CMOS level): 2.75 mW
•
TTL compatible I/O
•
512 refresh cycles/8 ms (MAX.)
•
Available for auto-refresh and self-refresh
modes
•
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
CMOS 512K (64K
×
8) Pseudo-Static RAM
DESCRIPTION
The LH5P860 is a 512K-bit Pseudo-Static RAM or-
ganized as 65,536
×
8 bits. It is fabricated using sili-
con-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
RFSH
NC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
R/W
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5P860-1
TOP VIEW
Figure 1. Pin Connections for DIP and
SOP Packages
1
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
