LRS1331
Data Sheet
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball 8 mm × 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 90 ns
– Operating current (MAX.)
(The current for F-V
CC
pin and F-V
CCW
pin):
– Read: 25 mA (t
CYCLE
= 200 ns)
– Word write: 57 mA
– Block erase: 42 mA
– Standby current (the current for F-V
CC
pin): 15 µA
(MAX. F-RP
≤
GND ± 0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
Stacked Chip
16M Flash Memory and 4M SRAM
– Thirty-one 32K-word main blocks
– Bottom boot location
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM
– Access time (MAX.): 85 ns
– Operating current: 45 mA (MAX.)
– Standby current: 15 µA (MAX.)
– Data retention current: 2 µA (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as
1,048,576 × 16-bit flash memory and 262,144 × 16-bit
static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA
INDEX
TOP VIEW
1
A
B
C
D
E
F
G
H
NC
NC
2
NC
3
NC
A
16
4
A
11
A
8
5
A
15
A
10
T
1
T
2
6
A
14
A
9
7
A
13
8
A
12
9
F-GND
10
NC
DQ
7
DQ
5
11
NC
12
NC
DQ
15
S-WE
DQ
14
DQ
6
DQ
4
F-WE F-RY/
BY
S-A
17
DQ
13
T
4
GND F-RP
F-WP
DQ
12
S-CE
2
S-V
CC
F-V
CC
T
3
DQ
9
DQ
10
DQ
2
DQ
8
DQ
0
DQ
3
DQ
1
F-V
PP
F-A
19
DQ
11
NC
S-LB S-UB
S-OE
F-A
18
NC
NC
F-A
17
A
5
A
7
A
4
A
6
A
0
A
3
A
2
A
1
S-CE
1
NC
NC
NC
F-CE F-GND F-OE
NOTE:
All F-GND and S-GND pins are connected on the board.
Two NC pins at the corner are connected.
LRS1331-1
Figure 1. LRS1331 Pin Configuration
Data Sheet
1
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
