ULTRA LOW CURRENT CONSUMPTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.1.1_00
S-1206 Series
Standard Circuit
Input
Output
VIN
VOUT
*1
*2
CIN
CL
VSS
Single GND
GND
*1. A capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.1 µF or more can be used.
Figure 9
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (CIN) : 0.1 µF or more
Output capacitor (CL) : 0.1 µF or more (ceramic capacitor)
Caution A general series regulator may oscillate, depending on the external components selected. Check that
no oscillation occurs in the actual device using the above capacitor.
Selection of Input Capacitor (CIN) and Output Capacitor (CL)
The S-1206 Series requires an output capacitor between the VOUT pin and VSS pin for phase compensation.
Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1 µF or more in the entire temperature
range. However, when using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor with a capacitance
of 0.1 µF or more less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor.
The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is 0.1 µF or more for CIN and 0.1 µF or more for CL; however, when selecting
these capacitors, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.
Seiko Instruments Inc.
9
SII [ SEIKO INSTRUMENTS INC ]
