S-24CS08AFJ-TB-1G 参数 Datasheet PDF下载

Rev.4.4

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3. Data Transmission

2-WIRE CMOS SERIAL E

2

PROM

S-24CS01A/02A/04A/08A

Changing the SDA line while the SCL line is low, data is transmitted.

Changing the SDA line while the SCL line is high, a start or stop condition is recognized.

t

SU.DAT

t

HD.DAT

SCL

SDA

Figure 10 Data Transmission Timing

4. Acknowledge

The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down

the SDA line to acknowledge the receipt of the 8-bit data.

When an internal write cycle is in progress, the device does not generate an acknowledge.

SCL

(E PROM Input)

2

1

8

9

SDA

(Master Output)

SDA

2

(E PROM Output)

Start Condition

Acknowledge

Output

t

AA

t

DH

Figure 11 Acknowledge Output Timing

Seiko Instruments Inc.

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