ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
Rev.3.3_00
S-809xxC Series
(1) (2) (3) (4) (5)
B
VDD
Release volatage (+VDET
)
Hysteresis width (VHYS
)
A
Detection voltage (−VDET
)
Minimum operating voltage
VSS
VDD
Output from OUT pin
VSS
tD
Figure 15 Operation 2
2. Delay Circuit
The delay circuit delays the output signal from the time at which the power voltage (VDD) exceeds the
release voltage (+VDET) when VDD is turned on. The output signal is not delayed when the VDD goes below
the detection voltage (−VDET) (Refer to Figure 15). The delay time (tD) is determined by the time constant
of the built-in constant current (approx. 100 nA ) and the attached external capacitor (CD), and calculated
from the following equation.
tD (ms)=Delay coefficient×CD (nF)
Delay coefficient: (25°C)
Detection voltage −VDET ≤ 1.4 V
Detection voltage −VDET ≥ 1.5 V
Min. 0.57, Typ. 0.77, Max. 0.96
Nch open-drain output products: Min. 4.3,
CMOS output products: Min. 3.8,
Typ. 5.7,
Typ. 5.1,
Max. 7.2
Max. 6.4
Caution 1. When the CD pin is open, a double pulse shown in Figure 16 may appear at release. To
avoid the double pulse, attach 20 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin.
VOUT
time
Figure 16
2. Print circuit board layout should be made in such a way that no current flows into or
flows from the CD pin since the impedance of the CD pin is high, otherwise correct
delay time cannot be provided.
3. There is no limit for the capacitance of the external capacitor (CD) as long as the leakage
current of the capacitor can be ignored against the built-in constant current value.
Leakage current causes deviation in delay time. When the leakage current is larger
than the built-in constant current, no release takes place.
13
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
