HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR
S-812C Series
Capacitor C1 has an effect in minimizing output
V
fluctuation due to power-on, power line
IN
variation and load variation. Determine the
optimum value in the actual device.
Rev.1.0
VOUT
R1
V
OUT1
VIN
S-812C
Series
VSS
ON/OFF
C
L
C
IN
C1
GND
It is not also recommended to attach a
capacitor between the S-812 power source VIN
and VSS pins or between output VOUT and
VSS pins because output fluctuation or
oscillation at powering on might occur.
R2
Figure 13 Voltage Adjustment Circuit
Notice
•
Wiring patterns for VIN, VOUT and GND pins should be designed to hold low impedance.
When mounting an output capacitor, the distance from the capacitor to the VOUT pin and to the VSS pin
should be as short as possible.
•
Note that output voltage may increase when a voltage regulator is used at low load current (less than 1
µA).
•
At low load current less than 100µA output voltage may increase when the regulating operation is halted by
the ON/OFF pin.
•
To prevent oscillation, it is recommended to use the external components under the following conditions:
Equivalent Series Resistance (ESR): 10
Ω
or less when an output capacitor is used.
Input series resistance (RIN): 10
Ω
or less
•
A voltage regulator may oscillate when the impedance of the power supply is high and the input capacitor is
small or not connected.
•
The application condition for input voltage and load current should not exceed the package power
dissipation.
•
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
10
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
