AN315 参数 Datasheet PDF下载

AN315

R

OBUST

E

LECTRICAL

S

URGE

I

MMUNITY

F O R

P

O

E PD

S T H R O U G H

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N T E G R A T E D

P

R O T E C T I O N

1. Introduction

The Si3400 and Si3401 Power over Ethernet (PoE) powered device (PD) controllers are designed in an efficient

Silicon on Insulator (SOI) process technology, which enables the integration of a robust surge protection function.

Competitive PoE PD devices require external transient voltage suppressors (TVS), such as an SMAJ58A, to

provide surge protection. However, due to their inherently wider range of clamping voltage specifications, external

TVS-based protectors typically necessitate the use of 100 V processes for the PD controller device. This note

discusses some of the detailed considerations regarding the Si3400's proprietary surge protection circuitry that

enable the Si3400 and Si3401 devices to yield robust and standards-compliant electrical surge immunity when

used in Power over Ethernet powered device applications.

2. Traditional PD Surge Protection Considerations

As will be discussed later, surge currents of up to 5 A must be tolerated in PoE applications. The surge protector

most often used with PD controllers is an external SMAJ58A TVS diode (D1 in Figure 1).

To

RJ 45 &

Magnetics

VSS

VSS

B1

D1

VPOS

RDET

VCC

VSS

M1

Vout

Opto

802.3af

PD I/F

+

Switching

Regulator

RCLASS

VNEG

VSS

SWO

DET

FB

EROUT

B2

Figure 1. Traditional PoE PD Interface and Switching Regulator

(without High Voltage Device Integration)

For example, a standard SMAJ58A TVS from Diodes Incorporated has a maximum operating voltage of 58 V,

25 °C ratings of between 64.4 and 71.2 V at 1 mA, and a clamping voltage under 93.6 V at 4.3 A.

While it is possible to sort individual devices for tighter clamp voltage ratings, the typical maximum clamping

voltage (including temperature variations) when using this type of protector is close to 100 V. Consequently, most

PoE PD controllers are implemented in processes providing a 100 V breakdown voltage.

Rev. 0.2 10/06

Copyright © 2006 by Silicon Laboratories

Reg

AN315