C8051F016
25 MIPS, 32 kB Flash, 10-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 µC Core
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±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Voltage output
10 µsec settling time
16 programmable hysteresis values
Configurable to generate interrupts or reset
Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler; up to 21 interrupt sources
2304 bytes data RAM
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
16 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules
4 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
48-pin TQFP (standard lead and lead-free packages)
Lead-free package: C8051F016-GQ
Standard package: C8051F016
Memory
Two 12-Bit DACs
Digital Peripherals
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug
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On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Clock Sources
Package
Ordering Part Numbers
Supply Voltage: 2.7 to 3.6 V
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Typical operating current: 12.5 mA at 25 MHz
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Multiple power saving sleep and shutdown modes
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Temperature Range: –40 to +85 °C
VDD
VDD
DGND
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
RST
Digital Power
UART
SMBus
SPI Bus
Analog Power
5-Chnl
PCA
Boundary Scan
Debug HW
Reset
JTAG
Logic
VDD
Monitor
XTAL1
XTAL2
WDT
8
0
5
1
C
o
r
e
32 kB
FLASH
256 Byte
RAM
2048 Byte
XRAM
Timers
0,1,2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
C
R
O
S
S
B
A
R
S
W
I
T
C
H
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
External
Oscillator
Circuit
Internal
Oscillator
System Clock
SFR Bus
Port 3
Latch
VREF
DAC1
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
DAC0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
A
M
U
X
Prog
Gain
ADC
100 ksps
(10-Bit)
TEMP
SENSOR
CP0
CP1
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
5.5.2005
SILABS [ SILICON LABORATORIES ]
